The present invention relates to a method for performing a test case with at least one logic built-in-self-test (LBIST) engine on an integrated circuit. Further the present invention relates to an integrated circuit with a plurality of storage elements and/or logic circuits and at least one LBIST engine. In addition the present invention relates to a method for specifying an according integrated circuit with a LBIST engine.
Integrated semiconductor circuits include a plurality of storage elements and logic circuits. During the production the integrated circuits have to be tested in order to detect defects on the integrated circuit. An example of such a method is the level sensitive scan design (LSSD) test. Thereby a LSSD tester generates test patterns, which are scanned into scan chains formed by the storage elements. In another example built-in-self-test (BIST) engines or logic built-in-self-test (LBIST) engines form a part of the integrated circuit.
For the LBIST engine the integrated circuit has to provide a pseudo-random pattern generator (PRPG), a multiple input signature register (MISR), masking and weighting storage elements and a glue logic. The PRPG generates random patterns. Said random patterns are driven into the scan chains. The scan chain is formed by a plurality of storage elements. The results from the scan chains are serially compressed into the MISR. The length of the scan chain determines the time for the test case.
FIG. 4 illustrates a schematic diagram of a part of an integrated circuit under test with scan chains according to the prior art. The integrated circuit comprises a plurality of storage elements 10 and 12. In this example the storage elements 10 and 12 are of master-slave-types and include two flip-flop elements L1 and L2. The storage element 10 and 12 comprise a data output DO, a scan input SI, a scan output SO, at least one scan clock input SC and a mixed clock input MC. Additionally the storage element 10 comprises a data input DI and a functional clock input FC. The storage elements 10 are scan-able storage elements. The storage elements 12 are so-called scan-only storage elements. Said scan-only storage elements are used to store constant information necessary for the functionality of the system.
In a non-functional mode for testing and scanning purposes all storage elements 10 and 12 are connected serially to a scan chain 20 via their scan inputs SI and scan outputs SO.
Further the integrated circuit includes logic circuits 14. The input ports of the logic circuit 14 are connected to the data outputs DO of several storage elements 10 and 12. The output port of the logic circuit 14 is connected with one or more data inputs DI of another storage elements 10 and 12.
In a functional mode the functional clock inputs FC are running to clock the scan-able storage elements 10. In the non-functional mode the scan clock inputs SC are used to shift data through the storage elements 10 and 12 in the scan chain 20. The scan data is captured at the scan input SI and delivered to the scan output SO.
FIG. 5 illustrates a functional diagram of the integrated circuit with the LBIST engine according to the prior art. The integrated circuit includes a pseudo-random pattern generator (PRPG) 22, weighting storage elements 24, a weighting and phaseshift logic 26, N scan chains 28, masking storage elements 32, a masking logic 34 and a multiple input signature register (MISR) 36. Between the scan chains 28 are logic circuits 30. The scan chains 28 are formed by storage elements. The output of the storage elements in the scan chains 28 feed the logic circuits 30.
In this example the logic circuit 30 between the scan chain (0) and the scan chain (1) is fed by the storage elements in scan chain (0). The outputs of this logic circuit 30 are captured by the scan chain (1). For simplicity reasons the inputs of scan chain (0) and the outputs of scan chain (1) are not shown in FIG. 5. In reality the wiring connections between the scan chains 28 and the logic circuits 30 depend solely on the assignment of the storage elements to scan chains 28 and logic gates to logic circuits 30.
The PRPG 22 generates random patterns to be driven into the scan chains 28. The results from the scan chains 28 are serially compressed into the MISR 36 and read out after completion.
In the state of the art described above additional circuits are required for the LBIST engines on the integrated circuit. In the normal operation, i.e. in the functional mode, of the integrated circuit the LBIST engines remain idle. For example a typical integrated circuit has several LBIST engines. Every LBIST engine requires a lot of storage elements. The number of the storage elements depends on a predetermined test time.
It is an object of the present invention to provide an improved method and an according improved integrated circuit for performing LBIST test cases.